111 lines
3.5 KiB
C
111 lines
3.5 KiB
C
/* Copyright 2018 Jack Humbert
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* Copyright 2018 Yiancar
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*
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* This program is free sofare: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Sofare Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This library follows the convention of the AVR i2c_master library.
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* As a result addresses are expected to be already shifted (addr << 1).
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* I2CD1 is the default driver which corresponds to pins B6 and B7. This
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* can be changed.
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* Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
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* STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file.
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*/
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#pragma once
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#include "ch.h"
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#include <hal.h>
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#if defined(STM32F1XX) || defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32L0xx) || defined(STM32L1xx)
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#define USE_I2CV1
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#endif
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#ifdef I2C1_BANK
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#define I2C1_SCL_BANK I2C1_BANK
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#define I2C1_SDA_BANK I2C1_BANK
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#endif
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#ifndef I2C1_SCL_BANK
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#define I2C1_SCL_BANK GPIOB
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#endif
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#ifndef I2C1_SDA_BANK
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#define I2C1_SDA_BANK GPIOB
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#endif
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#ifndef I2C1_SCL
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#define I2C1_SCL 6
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#endif
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#ifndef I2C1_SDA
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#define I2C1_SDA 7
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#endif
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#ifdef USE_I2CV1
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#ifndef I2C1_OPMODE
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#define I2C1_OPMODE OPMODE_I2C
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#endif
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#ifndef I2C1_CLOCK_SPEED
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#define I2C1_CLOCK_SPEED 100000 /* 400000 */
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#endif
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#ifndef I2C1_DUTY_CYCLE
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#define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
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#endif
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#else
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// The default PAL alternate modes are used to signal that the pins are used for I2C
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#ifndef I2C1_SCL_PAL_MODE
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#define I2C1_SCL_PAL_MODE 4
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#endif
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#ifndef I2C1_SDA_PAL_MODE
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#define I2C1_SDA_PAL_MODE 4
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#endif
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// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
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// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
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#ifndef I2C1_TIMINGR_PRESC
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#define I2C1_TIMINGR_PRESC 15U
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#endif
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#ifndef I2C1_TIMINGR_SCLDEL
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#define I2C1_TIMINGR_SCLDEL 4U
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#endif
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#ifndef I2C1_TIMINGR_SDADEL
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#define I2C1_TIMINGR_SDADEL 2U
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#endif
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#ifndef I2C1_TIMINGR_SCLH
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#define I2C1_TIMINGR_SCLH 15U
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#endif
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#ifndef I2C1_TIMINGR_SCLL
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#define I2C1_TIMINGR_SCLL 21U
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#endif
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#endif
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#ifndef I2C_DRIVER
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#define I2C_DRIVER I2CD1
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#endif
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typedef int16_t i2c_status_t;
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#define I2C_STATUS_SUCCESS (0)
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#define I2C_STATUS_ERROR (-1)
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#define I2C_STATUS_TIMEOUT (-2)
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void i2c_init(void);
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i2c_status_t i2c_start(uint8_t address);
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i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
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i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
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i2c_status_t i2c_transmit_receive(uint8_t address, uint8_t * tx_body, uint16_t tx_length, uint8_t * rx_body, uint16_t rx_length);
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i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
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i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
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void i2c_stop(void);
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